This application relies for priority on Korean Patent Application No. 2000-63184, filed on Oct. 26, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to nonvolatile storage devices, and, in particular, to a flash memory device with an improved program algorithm capable of reducing program time.
Generally, semiconductor memory devices for storing data are classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. The volatile semiconductor memory devices lose their data at power-off, and the nonvolatile semiconductor memory devices maintain their data even at power-off. Therefore, the nonvolatile semiconductor memory devices have been widely used at applications in which power can be unexpectedly interrupted.
The nonvolatile semiconductor memory devices comprise electrically erasable and programmable ROM cells which are referred to as xe2x80x9cflash EEPROM cellsxe2x80x9d or xe2x80x9cflash memory cells.xe2x80x9d FIG. 1 shows a cross-sectional view of the flash memory cell. The flash memory cell, as illustrated in FIG. 1, has a semiconductor substrate (or bulk) 1 of a first conductive type (e.g., P type), source and drain regions 2 and 3 of a second conductive type (e.g., N type) spaced apart relative to each other, a floating gate 6 storing charges and placed over a channel region between the source and drain regions 2 and 3, with a thin insulation film 4 having a thickness of about 100 xc3x85 interposed therebetween, and a control gate 8 placed over the floating gate 6, with another insulation film 7 interposed therebetween. The control gate 8 is connected to a word line.
The table below shows typical source, drain, control gate and bulk voltages according to program, read, erase and erase repair operations of a flash memory cell.
The program operation of the flash memory cell is performed by biasing a substrate 1 and a source region 2 with a ground voltage and the drain region 3 with a positive voltage (e.g., 5 Vxcx9c6 V) appropriate to generate hot electrons. According to this program operation, a sufficient amount of charges are stored in the floating gate 6, thus the floating gate 8 has a negative voltage. This means that a threshold voltage of the programmed flash memory cell is increased when performing the read operation.
During the read operation where a positive voltage (e.g., 4.5 V) is applied to the control gate 8 and the ground voltage is applied to the source region 3, no channel of the programmed memory cell is formed. That is, current from the drain region 3 to the source region through the channel is cut off. At this time, the memory cell has an xe2x80x9coffxe2x80x9d state, and a threshold voltage thereof is distributed in a range of 6 V to 7 V, as illustrated in FIG. 2.
Flash memory cells in a sector are simultaneously erased by a F-N (Flower-Nordheim) tunneling mechanism. According to the F-N tunneling mechanism, a negative high voltage (e.g., xe2x88x9210 V) is applied to the control gate 9 and a positive voltage (e.g., 5 V to 10 V) is applied to the semiconductor substrate 1. At this time, as seen from the table, the source and drain regions 2 and 3 are maintained at a floating state of high-impedance. An erase operation of this bias condition is named a xe2x80x9cNegative Gate and Bulk Erase (NGBE)xe2x80x9d operation. By such a bias condition, an electric field of about 6xcx9c7 millivolts (mV)/cm is formed across the tunneling oxide film 4 or between the control gate 8 and the semiconductor substrate 1, and negative charges accumulated in the floating gate 6 are emitted via the tunneling oxide layer 4 to the semiconductor substrate 2 via a mechanism such as the F-N tunneling. This causes the effective threshold voltage of the cell to be reduced to within a range of about 1 V to 3 V. As its effective threshold voltage is reduced, the cell transistor enters a conductive state (i.e., an xe2x80x9conxe2x80x9d state) when a read voltage is applied to the control gate 8 during the read operation.
Various erase methods associated with the flash memory device are disclosed in U.S. Pat. No. 5,781,477 entitled xe2x80x9cFLASH MEMORY SYSTEM HAVING FAST ERASE OPERATIONxe2x80x9d, U.S. Pat. No. 5,132,935 entitled xe2x80x9cERASURE OF EEPROM MEMORY ARRAYS TO PREVENT OVER-ERASED CELLSxe2x80x9d, U.S. Pat. No. 5,220,533 entitled xe2x80x9cMETHOD AND APPARATUS FOR PREVENTING OVERERASURE IN A FLASH CELLxe2x80x9d, U.S. Pat. No. 5,513,193 entitled xe2x80x9cNON-VOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CHECKING THE THRESHOLD VALUE OF MEMORY CELLSxe2x80x9d, and U.S. Pat. No. 5,805,501 entitled xe2x80x9cFLASH MEMORY DEVICE WITH MULTIPLE CHECKPOINT ERASE SUSPEND LOGICxe2x80x9d.
The erase verify operation determines whether all memory cells in a sector after the NGBE operation exist in a target threshold voltage range (e.g., 1 Vxcx9c3 V) corresponding to the on state. The erase verify operation is performed by biasing the control gate with an erase verify voltage of about 3 V and the drain region with a voltage of about 5 V. At this time, the source region and the semiconductor substrate are grounded.
Commonly, a threshold voltage of the erased flash memory cell is distributed in a range of 1 V to 3 V. Nevertheless when all memory cells of the sector are simultaneously erased, a threshold voltage of a flash memory cell may be lowered below 1 V. Such a flash memory cell is named xe2x80x9can over-erased memory cellxe2x80x9d. The over-erased memory cell(s) can be repaired by an erase repair operation (referred to as a post program operation or an over-erase repair operation), in which the threshold voltage of the over-erased cell is shifted in a target threshold voltage range (e.g., 1 Vxcx9c3 V) corresponding to the on state.
The erase repair operation is performed by biasing the source region and the semiconductor substrate of the over-erased memory cell with the ground voltage and the control gate thereof with a voltage of about 3 V. Under this bias condition, negative charges less than that of the program operation are accumulated in the floating gate. Thus, by performing the erase repair operation, the threshold voltage of the over-erased flash memory cell can be shifted in the target threshold voltage range of the on state as illustrated in FIG. 2.
In general, memory cells of the sector are erased according to a set of algorithms including a pre-program algorithm, a main erase algorithm and a post-program algorithm. The pre-program algorithm corresponds to the above-mentioned program process, and the post-program algorithm corresponds to the above-mentioned erase repair process. The main erase algorithm corresponds to the above-mentioned erase process. A flowchart illustrating a main erase algorithm according to the prior art is illustrated in FIG. 3.
In order to perform a sector (or block) erase operation, first, an address counter, an erase loop counter and a bulk step counter are initialized (S10). The address counter generates an address for appointing memory cells to be selected by the byte or word, the erase loop counter is used to limit loop times consisting of a set of NGBE and erase verify operations, and the bulk step counter is used to step a bulk voltage. After initializing, the NGBE and erase verify operations are performed in a subsequent step S20. The NGBE operation to a selected sector is performed during a predetermined period of time (e.g., 2xcx9c5 seconds) according to the above-mentioned bias condition.
After the NGBE operation, the erase verify operation is carried out which is to judge whether the threshold voltages of the erased memory cells are distributed below an upper limit value (e.g., 3 V) of a threshold voltage distribution corresponding to the on or erased state. Such an erase verify operation is identical to a read operation with the exception of a voltage applied to the control gate. If data bits of a byte or word unit read out according to the erase verify operation all are a logic xe2x80x9c1xe2x80x9d, then the erase verify operation is treated as a verify pass indicating that the threshold voltages of the selected memory cells exist in the threshold voltage distribution corresponding to the erased state. If at least one data bit is a logic xe2x80x9c0xe2x80x9d, the erase verify operation is treated as verify fail. In this case, the erase operation is again performed.
Before the erase operation is again carried out, it is determined whether a current erase loop value exceeds a maximum erase loop value (S40). If so, the main erase algorithm ends as erase fail. If not, the loop counter is increased by 1. To accelerate the NGBE operation, the bulk voltage is stepped by a predetermined voltage (e.g., 0.2 Vxcx9c03. V) through step S50. The NGBE operation is carried out using the bulk voltage thus increased in the step S20. As the bulk voltage is increased, on the whole, a threshold voltage distribution of a memory cell is shifted left along an X-axis of FIG. 2 in proportion to an increased magnitude of the bulk voltage. The above-described steps S20 to S50 are repeated until the threshold voltages of all memory cells are shifted below the maximum limit value of the threshold voltage distribution corresponding to the erased state.
According to the main erase algorithm of the prior art using the bulk voltage stepping method, in case the NGBE operation is carried out successfully, all memory cells have a threshold voltage distributed below the maximum limit value of the threshold voltage distribution corresponding to the erased state. In case several memory cells with bad erase property or slow erase speed exist in a sector to be erased, the main erase algorithm of the prior art has the following problem.
In order to shift threshold voltages of memory cells with the bad erase property in the threshold voltage distribution of the erased state, as described above, the bulk voltage is increased and then a next NGBE operation is performed using the increased bulk voltage. However, threshold voltages of memory cells, which exist in the threshold voltage distribution of the erased state, are shifted left increasingly in proportion to the increased magnitude of the bulk voltage. As a result, threshold voltages of memory cells placed near or at a minimum limit value are shifted below the minimum limit value of the threshold voltage distribution corresponding to the erased state. That is, the number of over-erased memory cells is increased. This causes an undesirable increase in the time necessary for the post-program algorithm to be performed after the main erase algorithm. In other words, the time for an overall erase operation is increased.
It is therefore an object of the invention to provide a flash memory device and an erase method thereof that are capable of reducing overall erase time.
It is another object of the invention to provide a flash memory device and an erase method thereof that can minimize over-erasing of flash memory cells during an erase operation.
In order to attain the above objects, according to an aspect of the present invention, there is provided a novel erase method for erasing an array of memory cells, arranged in rows and columns, through a set of erase and erase verify operations. This method includes the first step of performing the erase operation according to a gradually increased bulk voltage during a first erase discrimination period in which a representing number of failed erase verify cells is higher than a first predetermined value; and the second step of performing the erase operation according to a fixed bulk voltage during a second erase discrimination period in which the so-called xe2x80x98fail numberxe2x80x99 of the erase verify operation is between the first predetermined value and a second predetermined value.
In this embodiment, the first step comprises the steps of repeatedly performing an erase verify operation on ones of the memory cells after simultaneously erasing the memory cells according to a predetermined bulk voltage; generating a pass/fail signal indicating that the erase verify operation has failed; and increasing the bulk voltage when a determined number of the pass/fail signals is higher than the first predetermined value and performing the erase operation on the array.
In this embodiment, the second step comprises the steps of repeatedly performing an erase verify operation on ones of the memory cells after simultaneously erasing the memory cells according to the fixed bulk voltage; generating a pass/fail signal indicating that the erase verify operation has failed; and performing the erase operation on the array according to the fixed bulk voltage when a determined number of the pass/fail signals is higher than the second predetermined value.
In this embodiment, the second value is less than the first value and is zero or a positive integer.